|
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|
|
| LEADER |
00000pam a2200000 4500 |
| 001 |
28592 |
| 003 |
MY-KLNDU |
| 005 |
20241218082610.0 |
| 020 |
0 |
0 |
|a 9781420051544 (alk. paper)
|
| 020 |
0 |
0 |
|a 1420051547 (alk. paper)
|
| 035 |
|
|
|a 0000036089
|
| 039 |
|
9 |
|a 200911181403
|b VLOAD
|c 200911181220
|d VLOAD
|y 200910091814
|z VLOAD
|
| 090 |
0 |
0 |
|a TK7868 .D5
|b C395 2007
|
| 100 |
1 |
0 |
|a Cavanagh
|h Joseph J.F.
|
| 245 |
1 |
0 |
|a Verilog HDL
|b digital design and modeling
|c Joseph Cavanagh
|
| 260 |
0 |
0 |
|a Boca Raton, FL
|b CRC Press
|c c2007
|
| 300 |
|
|
|a xviii, 900p.
|b ill.
|c 26cm.
|
| 500 |
0 |
0 |
|a Includes index.
|
| 591 |
|
|
|a 0000006752
|b 04/12/08
|c 0200-07
|d 1
|e RM251.85
|f 1
|g 251.85
|h YUHA Associates Sdn.Bhd
|
| 592 |
|
|
|a 075845
|b 06/03/09
|c RM235.12
|d 1
|e 235.12
|
| 650 |
0 |
0 |
|a Digital electronics
|
| 650 |
0 |
0 |
|a Logic circuits
|x Computer-aided design
|
| 650 |
0 |
0 |
|a Verilog (Computer hardware description language)
|
| 999 |
|
|
|a vtls000038704
|c 28592
|d 28592
|
