Chip design for submicron VLSI CM1 layout and simulation

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Bibliographic Details
Main Author:	Uyemura 1952-
Format:	Book
Published:	Toronto Thomson/Nelson 2006
Subjects:	Matel oxide semiconductors,Complementary > Design and construction Integrated circuits > Very large scale integration > Design and construction
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MARC


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100	1	0	\|a Uyemura \|h John P. \|d 1952-
245	1	0	\|a Chip design for submicron VLSI \|b CM1 layout and simulation \|c John P.Uyemura
260	0	0	\|a Toronto \|b Thomson/Nelson \|c 2006
300			\|a xvi,411p. \|b ill \|c 25cm \|e 1 CD-ROM (4 3/4in)
500			\|a CD available for loan
504	0	0	\|a Includes bibliographical references and index
650	0	0	\|a Matel oxide semiconductors,Complementary \|x Design and construction
650	0	0	\|a Integrated circuits \|x Very large scale integration \|x Design and construction
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