VHDL a logic synthesis approach
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| Main Author: | |
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| Format: | Book |
| Language: | English |
| Published: |
London, UK
Chapman & Hall
1997
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| 001 | 46831 | ||
| 003 | MY-KLNDU | ||
| 005 | 20241219005012.0 | ||
| 008 | 121009 1997 xxka i 000 0 eng d | ||
| 020 | |a 0412616505 | ||
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| 040 | |a UPNM | ||
| 090 | |a TK 7885.7 |b .N39 1997 | ||
| 100 | 1 | |a Naylor, David | |
| 245 | 1 | 0 | |a VHDL |b a logic synthesis approach |c David Naylor and Simon Jones |
| 260 | |a London, UK |b Chapman & Hall |c 1997 | ||
| 300 | |a x, 339 p. |b ill. |c 24 cm. | ||
| 500 | |a Includes index | ||
| 650 | 0 | |a VHDL (computer hardware description language) | |
| 650 | 0 | |a Logic design |x data processing | |
| 650 | 0 | |a Computer-aided design | |
| 700 | 1 | |a Jones, Simon | |
| 999 | |a vtls000047604 |c 46831 |d 46831 | ||