Modeling, synthesis, and rapid prototyping with the Verilog HDL

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Bibliographic Details
Main Author: Ciletti, Michael D. (Author)
Format: Book
Language:English
Published: Upper Saddle River, N.J. Prentice Hall 1999
Subjects:
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LEADER 00000nam a2200000 c 4500
001 90027
003 MY-KLNDU
005 20241219044934.0
008 221104 19991999xxua b 001 0 eng d
020 |a 9780139773983 (hbk) 
039 9 |a 202307170827  |b rafizah  |c 202211041302  |d VLOAD  |c 202203311052  |d hainim  |y 202108171222  |z zubir 
040 |a MY-KlNDU  |b eng  |c MY-KlNDU  |e rda 
050 |a TK 7885.7 
090 |a TK 7885.7  |b .C55 1999 
100 1 |a Ciletti, Michael D.  |e author 
245 1 0 |a Modeling, synthesis, and rapid prototyping with the Verilog HDL  |c Michael D. Ciletti 
264 1 |a Upper Saddle River, N.J.  |b Prentice Hall  |c 1999 
264 4 |a © 1999 
300 |a xxii, 727 pages  |b illustration  |c 25 cm +  |e 2 DVD (4 3/4 in.) 
336 |a text  |2 rdacontent 
336 |a text  |2 rdacontent  |3 book 
337 |a unmediated  |2 rdamedia 
337 |a computer  |2 rdamedia  |3 DVD 
338 |a volume  |2 rdacarrier 
338 |a computer disc  |2 rdacarrier  |3 DVD 
500 |a The book is accompanied by 1 CD ROM bearing the same call number and available at the circulation counter 
504 |a Includes bibliographical references and index 
592 |c Hadiah & sumbangan 
650 0 |a Verilog (Computer hardware description language) 
650 0 |a Rapid prototyping 
999 |a vtls000100352  |c 90027  |d 90027