Network-on-chip the next generation of system-on-chip integration
This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques,...
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| Main Authors: | , |
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| Format: | Book |
| Language: | English |
| Published: |
Boca Raton, FL
CRC Press Taylor & Francis Group
[2015]
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| Subjects: | |
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| Call Number : | TK 5105.546 .K86 2015 |
MARC
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| 020 | |a 9781466565265 (Hardback) | ||
| 020 | |a 1466565268 (Hardback) | ||
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| 040 | |a UPNM |b eng |c UPNM |e rda | ||
| 090 | |a TK 5105.546 |b .K86 2015 | ||
| 100 | 1 | |a Kundu, Santanu |e author | |
| 245 | 1 | 0 | |a Network-on-chip |b the next generation of system-on-chip integration |c Santanu Kundu, Santanu Chattopadhyay |
| 264 | 1 | |a Boca Raton, FL |b CRC Press |b Taylor & Francis Group |c [2015] | |
| 264 | 4 | |c © 2015 | |
| 300 | |a xvii, 369 pages |b illustrations |c 24 cm | ||
| 336 | |a text |2 rdacontent | ||
| 337 | |a unmediated |2 rdamedia | ||
| 338 | |a volume |2 rdacarrier | ||
| 400 | 0 | |a Santanu Kundu | |
| 504 | |a Includes bibliographical references and index | ||
| 505 | 0 | |a 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends | |
| 520 | |a This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends | ||
| 592 | |a INV/98511 |b 9/1/2016 |c RM 573.07 |h YUHA | ||
| 650 | 0 | |a Networks on a chip | |
| 700 | 1 | |a Chattopadhyay, Santanu |e author | |
| 999 | |a vtls000056067 |c 98496 |d 98496 | ||